Calculate the approximate switching time that is obtained if the output is loaded by a capacitance of 0.2 pF due to interconnections and the inputs of other gates, in the given CMOS inverter circuit.

The circuit shown in Figure B2 (in the attachment) is of a CMOS inverter driving a capacitive load. VDD represents logic level "1" and zero volts logic level "0". M1 is an nMOS device and M2 is a pMOS device.

Calculate the approximate switching time that is obtained if the output is loaded by a capacitance, CL, of 0.2 pF due to interconnections and the inputs of other gates.

Please refer to the attachment for full details.

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